Modern electronic devices and systems, for example, computer processors, mobile telephones, personal digital assistants (PDAs), digital cameras, and combinations thereof currently rely on logic (e.g., controller) and storage (e.g., memory) circuits fabricated with semiconductor materials to form integrated circuits called chips.
Random access memory (RAM) is an example of a common storage circuit that permits data to be accessed in any order (e.g., randomly), regardless of the data's physical location in the memory chip and regardless of whether or not the data is related to previous data. Two types of RAM include Static RAM (SRAM), which typically does not need to be refreshed, and Dynamic RAM (DRAM), which typically needs to be refreshed. SRAM is usually faster, but more expensive than DRAM. Both SRAM and DRAM are typically volatile in the sense that they lose data when power is removed from the memory chip.
Complementary Metal Oxide Semiconductor (CMOS) technology is widely used in such logic and storage circuitry because they provide relatively high speed and relatively low power. CMOS circuits employ P-channel field effect transistors (PFETs) and N-channel field effect transistors (NFETs).
Recent advances in CMOS fabrication technology have reduced the physical sizes of the FETs. FET supply voltages (VDD) have been reduced to save power and to accommodate requirements of the reduction in the physical sizes of the FETs. FET threshold voltages (VT) have been reduced to mitigate performance degradation effects of reduced FET gate voltages resulting from the reduction of supply voltages.
Due to the reduced physical sizes and the reduction in threshold voltages (VT) of the FETs, threshold voltage (VT) shifts in PFETs caused by negative bias temperature instability (NBTI) are becoming a significant reliability issue. NBTI reduces transistor performance parameters (e.g., drain current, transconductance, threshold voltage (VT), capacitance, etc.).
The threshold voltage (VT) shifts in PFETs caused by NBTI causes an increase in the absolute value of the threshold voltage (VT) in a PFET. The increase in the threshold voltage (VT) in a PFET is a function of the gate voltage relative to the source and drain voltages on the PFET. The threshold voltage (VT) shifts in PFETs caused by NBTI accumulate over time during which the PFET is in a voltage stress condition, which is a condition known as aging.
A PFET is in an NBTI voltage stress condition when the source and the drain of the PFET are both at a logic “high” voltage level and the gate is at a logic “low” voltage level, such as when a PFET is biased in an inversion state (e.g., VS=VD=VB=VDD and VG=0). For example, in a CMOS chip, employing current technology, having a 1.2 volt supply voltage, a PFET is in an NBTI voltage stress condition when its source and its drain are at 1.2 volt and its gate is at ground (i.e. 0 volts). When the gate is logic “high” and the source is logic “high,” the PFET tends to recover somewhat from NBTI caused VT increase. A balanced duty cycle for PFETs (50% in an NBTI voltage stress condition, 50% not in an NBTI voltage stress condition) would produce varying stress on the PFET. A full duty cycle for PFETs (100% in an NBTI voltage stress condition) would produce maximum stress on the PFET. A minimum or no duty cycle for PFETs (100% not in an NBTI voltage stress condition) would produce little or no stress on the PFET.
Several methods attempt to address the problem associated with the threshold voltage (VT) shifts in PFETs caused by NBTI. Some methods use CMOS fabrication process techniques to minimize the amount of threshold voltage (VT) shift that occurs to minimize the number of defective chips. Other methods screen the chips after the CMOS fabrication process to separate the chips with defects from chips without defects.
Present CMOS fabrication process techniques employ a thinner dielectric material, such as oxides, used for the gate terminal of the PFET. However, thinning dielectric material has made the threshold voltage (VT) shifts in PFETs caused by NBTI more significant as an overall percentage of the normal threshold voltage (VT) variability. Environmental conditions such as high temperature also encourage threshold voltage (VT) shifts in PFETs caused by NBTI.
In current CMOS fabrication designs (e.g., 65 nm node), typical threshold voltage (VT) shift caused by NBTI may be 30 to 40 mV (millivolts) for a 50% duty cycle (i.e., the PFET spends half of the time in an NBTI voltage stress condition and half of its time not in an NBTI voltage stress condition) of the PFET. However, the threshold voltage (VT) shift in PFETs caused by NBTI may be 80 to 90 mV if the duty cycle is close to 100% (i.e., the PFET is almost always in an NBTI voltage stress condition). If an almost 0% duty cycle exists (i.e., the PFET is almost never in an NBTI voltage stress condition), virtually no threshold voltage (VT) shift in PFETs caused by NBTI occurs.
A number of situations can cause the duty cycle of a particular PFET to be significantly higher than 50%, of which one example is SRAM. For example, during normal operation of an electronic system, some storage elements, such as SRAM, may be written into and seldom if ever change, causing some of the PFETs to remain almost constantly in a voltage condition that causes threshold voltage (VT) shifts in PFETs caused by NBTI to accumulate. For example, operating system code is copied from nonvolatile storage such as a disk into an on-chip storage element, such as a memory array, in an electronic system, such as a computer, and is normally never changed for the entire time the computer is operating. Furthermore, it is likely that the operating system code is stored into the same locations in the storage element each time the computer is restarted. Therefore, threshold voltage (VT) shift in PFETs caused by NBTI is a significant threat to SRAM reliability.
NBTI also causes what might have been marginal, but operative, memory storage locations to become failing storage locations, such as degrading the READ stability of SRAM. For example, in a memory array (e.g., SRAM, or DRAM), an array built in self-test (ABIST) controller is commonly applied during testing of the chip.
An array built in self-test (ABIST) controller may be used during burn-in stress conditions (e.g., elevated temperature and/or supply voltage), such as a high temperature operating life (HTOL) test, to identify defects in a chip, such as a memory array (e.g., SRAM, or DRAM). The increased temperature and supply voltage conditions applied during burn-in increases the rate of degradation due to threshold voltage (VT) shifts in PFETs caused by NBTI. During burn-in, the ABIST controller generates data patterns that are sent to the memory array. ABIST checks output data patterns from the memory array against data pattern results expected from a memory array having no defect. Applying the generated data patterns to the memory array stresses the memory array, looking for defect types with various disturb data patterns. Some sets of ABIST data patterns result in a duty cycle near 100% for at least some PFETs in the memory array. Some electronic systems also run ABIST during restarts of the electronic systems. Restarts occur when the electronic system is powered up. Restarts on electronic systems also may be caused by manual intervention.
There are two conventional methods to screen the chips after the CMOS fabrication process to separate the chips with defects from chips without defects. A first screen method is a stress test or burn-in test, mentioned above, which stress the memory at a higher supply voltage Vdd and/or a higher temperature over time, which may be many hours. After the stress test, the chips are typically tested for functionality under a nominal supply voltage and temperatures. One disadvantage is the long time for completing the test.
A second screen method is a low voltage test, which tests the functionality of the chips below a design-specified minimum voltage. In the low voltage test, a data pattern is written to the chip at a voltage level below the design-specified minimum voltage. Then, the data pattern is read from the chip at the voltage level below the design-specified minimum voltage (i.e., a guard-band voltage gap). The data patterns written and read at the voltage level below the design-specified minimum voltage are compared to determine if the chip passes or fails the screen. An advantage of this method is that the method is much faster than the stress method. However, a disadvantage of this method is that the data patterns are written and read at the voltage level below the design-specified minimum voltage where the chip was not designed to function. Hence, this method causes more good parts to be screen out than otherwise should be screen out due to sensing margin and/or timing issues in the chip.
A similar voltage threshold (VT) shift in NFETs exists, although to a lesser degree than in PFETs in current technology, and is called positive bias temperature instability (PBTI). A NFET is in a PBTI voltage stress condition when a gate on the NFET is logic “high” and a source and a drain of the NFET are at a logic “low” voltage. Although, examples described herein illustrate how embodiments of the present invention overcomes adverse effects of threshold voltage (VT) shifts in PFETs caused by NBTI, similar embodiments are contemplated to reduce threshold voltage (VT) shifts in NFETs caused by PBTI.
Accordingly, there is a need for testing a memory device having field effect transistors subject to threshold voltage shifts caused by bias temperature instability.